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ISL8323, ISL8324, ISL8325
TM
Data Sheet
January 2002
FN6023
Low-Voltage, Single Supply, Dual SPST Analog Switches
The Intersil ISL8323-ISL8325 devices are precision, dual analog switches designed to operate from a single +2.7V to +12V supply. Targeted applications include battery powered equipment that benefit from the devices' low power consumption (5W), low leakage currents (100pA max), and fast switching speeds. Excellent RON matching and flatness maintain signal fidelity over the whole input range. The ISL8323/ISL8324/ISL8325 are dual single-pole/singlethrow (SPST) devices. The ISL8323 has two normally open (NO) switches; the ISL8324 has two normally closed (NC) switches; the ISL8325 has one NO and one NC switch and can be used as an SPDT. Table 1 summarizes the performance of this family. For higher performance, pin compatible versions, or SOT-23 packaged devices, see the ISL5120-23 data sheet.
TABLE 1. SUMMARY OF FEATURES ISL8323 Number of Switches SW 1 / SW 2 3.3V RON (Max) 3.3V tON / tOFF (Max) 5V RON (Max) 5V tON / tOFF (Max) Packages 2 NO / NO 175 400 / 125ns 60 150 / 100ns ISL8324 2 NC / NC 175 400 / 125ns 60 150 / 100ns 8 Ld SOIC ISL8325 2 NO / NC 175 400 / 125ns 60 150 / 100ns
Features
* Drop-in Replacements for MAX323 - MAX325 in Single Supply Applications up to 12V. * ON Resistance (RON). . . . . . . . . . . . . . . . . . . . 60 (Max) * RON Matching Between Channels. . . . . . . . . . . . . 2 (Max) * Low Charge Injection . . . . . . . . . . . . . . . . . . . . . . 5pC (Max) * Single Supply Operation . . . . . . . . . . . . . . . . . +2.7V to +12V * Low Power Consumption (PD) . . . . . . . . . . . . . . . . . . . .<5W * Low Leakage Current (Max at 85oC) . . . . . . . . . . . . . 5nA * Fast Switching Action - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150ns (Max) - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ns (Max) * Guaranteed Break-Before-Make (ISL8325 only) * Minimum 2000V ESD Protection per Method 3015.7 * TTL, CMOS Compatible
Applications
* Battery Powered, Handheld, and Portable Equipment - Cellular/Mobile Phones - Pagers - Laptops, Notebooks, Palmtops * Communications Systems - Military Radios - PBX, PABX * Test Equipment - Ultrasound - Electrocardiograph * Heads-Up Displays * Audio and Video Switching * Various Circuits - +3V/+5V DACs and ADCs - Sample and Hold Circuits - Digital Filters - Operational Amplifier Gain Switching Networks - High Frequency Analog Switching - High Speed Multiplexing - Integrator Reset Circuits
Related Literature
* Technical Brief TB363 Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved
ISL8323, ISL8324, ISL8325 Pinouts
(Note 1) ISL8323 (SOIC) TOP VIEW
NO1 1 COM1 2 IN2 3 GND 4 8 V+ 7 IN1 6 COM2 5 NO2
ISL8324 (SOIC) TOP VIEW
NC1 1 COM1 2 IN2 3 GND 4
8 V+ 7 IN1 6 COM2 5 NC2
ISL8325 (SOIC) TOP VIEW
NO1 1 COM1 2 IN2 3 GND 4 8 V+ 7 IN1 6 COM2 5 NC2
NOTE: 1. Switches Shown for Logic "0" Input.
Truth Table
ISL8323 LOGIC 0 1 SW 1,2 OFF ON ISL8324 SW 1,2 ON OFF ISL8325 SW 1 OFF ON SW 2 ON OFF
Ordering Information
PART NO. (BRAND) ISL8323IB ISL8323IB-T ISL8324IB ISL8324IB-T FUNCTION System Power Supply Input (+2.7V to +12V) Ground Connection Digital Control Input Analog Switch Common Pin Analog Switch Normally Open Pin Analog Switch Normally Closed Pin ISL8325IB ISL8325IB-T TEMP. RANGE (oC) -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 PACKAGE 8 Ld SOIC 8 Ld SOIC Tape and Reel 8 Ld SOIC 8 Ld SOIC Tape and Reel 8 Ld SOIC 8 Ld SOIC Tape and Reel PKG. NO. M8.15 M8.15 M8.15 M8.15 M8.15 M8.15
NOTE: Logic "0" 0.8V. Logic "1" 2.4V.
Pin Descriptions
PIN V+ GND IN COM NO NC
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ISL8323, ISL8324, ISL8325
Absolute Maximum Ratings
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V Input Voltages IN, NO, NC, COM (Note 2) . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Continuous Current (NO, NC, or COM) . . . . . . . . . . . . . . . . . . 30mA Peak Current NO, NC, or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . 100mA ESD Rating (Per MIL-STD-883 Method 3015). . . . . . . . . . . . . .>2kV
Thermal Information
Thermal Resistance (Typical, Note 3) JA (oC/W) 8 LD SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . 170 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Moisture Sensitivity (See Technical Brief TB363) All Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1 Maximum Storage Temperature Range . . . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range ISL832XIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 2. Signals on NC, NO, COM, or IN exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified TEST CONDITIONS TEMP (oC) Full MIN (NOTE 5) 0 -0.1 -5 -0.1 -5 -0.2 -10 2 2.7 -1 0.0001 TYP 0.8 7 10 72 -85 9 9 22 MAX (NOTE 5) UNITS V+ 60 75 2 4 8 0.1 5 0.1 5 0.2 10 150 240 100 150 5 12 1 V nA nA nA nA nA nA ns ns ns ns ns pC dB dB pF pF pF V A
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON RON Matching Between Channels, RON RON Flatness, RFLAT(ON) NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM OFF Leakage Current, ICOM(OFF) COM ON Leakage Current, ICOM(ON) DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF Break-Before-Make Time Delay (ISL8325), tD Charge Injection, Q OFF Isolation Crosstalk (Channel-to-Channel) COM OFF Capacitance, CCOM(OFF) COM ON Capacitance, CCOM(ON) Power Supply Range Positive Supply Current, I+
V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3.5V, See Figure 5 V+ = 5V, ICOM = 1.0mA, VNO or VNC= 3V V+ = 5V, ICOM = 1.0mA, VNO or VNC = 1V, 2V, 3V V+ = 5.5V, VCOM = 1V, 4.5V, VNO or VNC = 4.5V, 1V, Note 6 V+ = 5.5V, VCOM = 4.5V, 1V, VNO or VNC = 1V, 4.5V, Note 6 V+ = 5.5V, VCOM = 5V, or VNO or VNC = 5V, Note 6
25 Full 25 Full Full 25 Full 25 Full 25 Full
VNO or VNC = 3V, RL =1k , CL = 35pF, VIN = 0 to 3V, See Figure 1 VNO or VNC = 3V, RL =1k , CL = 35pF, VIN = 0 to 3V, See Figure 1 RL = 300 , CL = 35pF, VNO = VNC = 3V, VIN = 0 to 3V, See Figure 3 CL = 1.0nF, VG = 0V, RG = 0, See Figure 2 RL = 50, CL = 5pF, f = 1MHz, See Figure 4 RL = 50, CL = 5pF, f = 1MHz, See Figure 6 f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7
25 Full 25 Full Full 25 25 25 25 25 25 Full
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7
POWER SUPPLY CHARACTERISTICS V+ = 5.5V, VIN = 0V or V+, all channels on or off Full
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ISL8323, ISL8324, ISL8325
Electrical Specifications - 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified (Continued) TEST CONDITIONS TEMP (oC) Full Full MIN (NOTE 5) 2.4 TYP MAX (NOTE 5) UNITS 0.8 V V
PARAMETER DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH NOTES: 4. VIN = input voltage to perform proper function.
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at 25oC.
Electrical Specifications - 3.3V Supply
Test Conditions: V+ = +3.0V to +3.6V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified TEST CONDITIONS TEMP (oC) Full MIN (NOTE 5) 0 2 -1 TYP MAX (NOTE 5) UNITS V+ 175 275 400 500 125 175 5 1 V ns ns ns ns ns pC A
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF Break-Before-Make Time Delay (ISL8325), tD Charge Injection, Q Positive Supply Current, I+
V+ = 3V, ICOM = 1.0mA, VNO or VNC = 1.5V
25 Full
VNO or VNC = 1.5V, RL =1k, CL = 35pF, VIN = 0 to 3V VNO or VNC = 1.5V, RL =1k, CL = 35pF, VIN = 0 to 3V RL = 300, CL = 35pF, VNO or VNC = 1.5V, VIN = 0 to 3V CL = 1.0nF, VG = 0V, RG = 0 V+ = 3.6V, VIN = 0V or V+, all channels on or off
25 Full 25 Full Full 25 Full
POWER SUPPLY CHARACTERISTICS
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ISL8323, ISL8324, ISL8325 Test Circuits and Waveforms
3V LOGIC INPUT 50% 0V tOFF SWITCH INPUT VNO 90% SWITCH OUTPUT 0V tON SWITCH INPUT VOUT 90% LOGIC INPUT NO or NC COM IN GND RL 1k CL 35pF VOUT tr < 20ns tf < 20ns V+ C
Logic input waveform is inverted for switches that have the opposite logic sense.
Repeat test for all switches. CL includes fixture and stray capacitance. RL V OUT = V (NO or NC) -----------------------------R L + R ( ON ) FIGURE 1B. TEST CIRCUIT
FIGURE 1A. MEASUREMENT POINTS FIGURE 1. SWITCHING TIMES
V+
C
SWITCH OUTPUT VOUT
VOUT
RG
NO or NC
COM
VOUT
V+ LOGIC INPUT ON OFF 0V Q = VOUT x CL ON VG GND IN CL
LOGIC INPUT
FIGURE 2A. MEASUREMENT POINTS FIGURE 2. CHARGE INJECTION
FIGURE 2B. TEST CIRCUIT
V+ 3V LOGIC INPUT 0V VNX 90% 0V IN2 SWITCH OUTPUT VOUT2 90% 0V LOGIC INPUT GND
NO1
C
VOUT1 COM1 VOUT2 RL1 300 CL1 35pF
NC2
SWITCH OUTPUT VOUT1
COM2 IN1 RL2 300
CL2 35pF
tD
tD
CL includes fixture and stray capacitance. FIGURE 3A. MEASUREMENT POINTS (ISL8325 ONLY) FIGURE 3B. TEST CIRCUIT (ISL8325 ONLY)
FIGURE 3. BREAK-BEFORE-MAKE TIME
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ISL8323, ISL8324, ISL8325 Test Circuits and Waveforms (Continued)
V+ C SIGNAL GENERATOR RON = V1/1mA
NO or NC NO or NC
V+ C
VNX INX 0V or 2.4V 1mA V1 IN 0.8V or 2.4V
ANALYZER RL
COM
GND
COM
GND
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. RON TEST CIRCUIT
V+ C V+ C SIGNAL GENERATOR
NO1 or NC1 COM1
50
NO or NC
IN1 0V or 2.4V IN2 0V or 2.4V INX IMPEDANCE ANALYZER
COM
0V or 2.4V
ANALYZER RL
COM2
NO2 or NC2
GND
NC
GND
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCE TEST CIRCUIT
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ISL8323, ISL8324, ISL8325 Detailed Description
The ISL8323-ISL8325 dual analog switches offer precise switching capability from a single 2.7V to 12V supply with low on-resistance and high speed operation. The devices are especially well suited to portable battery powered equipment thanks to the low operating supply voltage (2.7V), low power consumption (5W), low leakage currents (100pA max), and the small SOIC packaging. High frequency applications also benefit from the wide bandwidth, and the very high off isolation and crosstalk rejection.
Power-Supply Considerations
The ISL832X construction is typical of most CMOS analog switches, except that they have only two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike switches with a 13V maximum supply voltage, the ISL832X 15V maximum supply voltage provides plenty of room for the 10% tolerance of 12V supplies, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 2.7V. It is important to note that the input signal range, switching times, and on-resistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance curves for details. V+ and GND also power the internal logic and level shifters. The level shifters convert the logic levels to switched V+ and GND signals to drive the analog switch gate terminals. This family of switches cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration.
Supply Sequencing And Overvoltage Protection
With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to GND (see Figure 8). To prevent forward biasing these diodes, V+ must be applied before any input signals, and input signal voltages must remain between V+ and GND. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1k resistor in series with the input (see Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. Adding a series resistor to the switch input defeats the purpose of using a low RON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see Figure 8). These additional diodes limit the analog signal from 1V below V+ to 1V above GND. The low leakage current performance is unaffected by this approach, but the switch resistance may increase, especially at low supply voltages.
Logic-Level Thresholds
This switch family is TTL compatible (0.8V and 2.4V) over a supply range of 3V to 11V (see Figure 12). At 12V the VIH level is about 2.5V. This is still below the TTL guaranteed high output minimum level of 2.8V, but noise margin is reduced. For best results with a 12V supply, use a logic family the provides a VOH greater than 3V. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation.
Leakage Considerations
Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of these diodes conducts if any analog signal exceeds V+ or GND. Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog-signal paths and V+ or GND.
OPTIONAL PROTECTION DIODE V+ OPTIONAL PROTECTION RESISTOR INX V NO or NC VCOM
GND OPTIONAL PROTECTION DIODE
FIGURE 8. OVERVOLTAGE PROTECTION
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ISL8323, ISL8324, ISL8325 Typical Performance Curves TA = 25oC, Unless Otherwise Specified
45 40 35 30 25 20 RON () 15 30 25 20 15 10 20 15 10 5 0 -40oC 2 4 6 VCOM (V) 8 10 12 85oC 85oC 25oC -40oC RON () V+ = 5V 85oC 25oC -40oC 25oC V+ = 12V ICOM = 1mA V+ = 3.3V 0.5 0.4 0.3 0.2 0.1 0 0.25 0.2 0.15 0.1 0.05 0 0.15 0.1 0.05 0 0 2 4 6 VCOM (V) 8 10 12 85oC -40oC V+ = 5V 25oC 85oC -40oC 25oC -40oC 85oC -40oC V+ = 12V 25oC 85oC 25oC ICOM = 1mA V+ = 3.3V
FIGURE 9. ON RESISTANCE vs SWITCH VOLTAGE
60 50 2.5 40 VINH AND VINL (V) 30 Q (pC) 20 10 V+ = 3.3V 0 -10 -20 0 2 4 6 VCOM (V) 8 10 12 0.5 2 V+ = 5V V+ = 12V 3.0
FIGURE 10. RON MATCH vs SWITCH VOLTAGE
VINH 2.0 -40oC 85oC
1.5
25oC -40oC 25oC VINL 85oC 3 4 5 6 7 8 V+ (V) 9 10 11
85oC
1.0
12
13
FIGURE 11. CHARGE INJECTION vs SWITCH VOLTAGE
100 VCOM = (V+) - 1V 90 80 RL = 1k
FIGURE 12. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
35 VCOM = (V+) - 1V RL = 1k 30 85oC tOFF (ns)
70 tON (ns) 60 85oC 50
25 -40oC
-40oC 40 30 25oC 20 2 3 4 5 6 7 V+ (V) 8 9 10 11 12 15 2 3 4 5 6 7 V+ (V) 8 9 -40oC 20
25oC
10
11
12
FIGURE 13. TURN - ON TIME vs SUPPLY VOLTAGE
FIGURE 14. TURN - OFF TIME vs SUPPLY VOLTAGE
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ISL8323, ISL8324, ISL8325 Die Characteristics
DIE DIMENSIONS: ISL832X: 54 mils x 28 mils (1370m x 710m) METALLIZATION: Type: Metal 1: AISi(1%) Thickness: Metal 1: 8kA Type: Metal 2: AISi (1%) Thickness: Metal 2: 10kA SUBSTRATE POTENTIAL (POWERED UP): GND PASSIVATION: Type: Silox Thickness: 13kA TRANSISTOR COUNT: ISL8323: 66 ISL8324: 66 ISL8325: 66 PROCESS: Si Gate CMOS
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ISL8323, ISL8324, ISL8325 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574
A1 B C D E

e
B 0.25(0.010) M C AM BS A1 0.10(0.004) C
e H h L N
0.050 BSC 0.2284 0.0099 0.016 8 0o 8o 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 8 0o 6.20 0.50 1.27
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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